eP9553(e) è un ricevitore combo a 3 porte a basso consumo HDMI/MHL/MCU conforme alle specifiche HDMI 1.4 e MHL 2.0. Il controller HDMI/MHL/CeC/CBUS on-chip semplifica l'utilizzo del chip da parte dell'utente. Gestisce automaticamente la commutazione del protocollo HDMI/MHL senza che l'utente debba sviluppare un firmware. Il controller CeC fornisce il ricetrasmettitore del livello fisico CeC e gestisce automaticamente il livello di protocollo. Il controller CBUS fornisce la traduzione tra la richiesta MHL RAP/RCP e il comando HDMI CeC in modo automatico. Il controller CBUS supporta anche il protocollo MSC UCP. Il chip supporta 1 porta HDMI/MHL dual mode (Porta 1) e 2 porte MHL (Porta 0 e Porta 2). Il chip supporta l'uscita video fino a 1080p 60 Hz. Il chip supporta anche uscite audio IIS e S/PDIF a 2 canali. Il chip integra switch di equalizzazione, core HDMI/MHL, motore HDCP e RAM eDID.

Caratteristica

•On-chip HDMI/MHL controller which manages HDMI and MHL Protocol automatically
•On-chip CeC controller which provides CeC Physical Layer Transceiver and handle the Protocol Layer without the need for user to develop firmware
•On-chip CBUS controller which provides the translation between the MHL RAP/RCP Request and the HDMI CeC Command
•On-chip CBUS controller which provides the MSC UCP Protocol
•On-chip HDMI/MHL Receiver core which is compliant with HDMI 1.4 and MHL 2.0 specifications
•On-chip HDCP engine which is compliant with HDCP 1.4 specification
•Support 1 HDMI/MHL dual mode port (Port 1) and 2 MHL ports (Port 0 and Port 2)
•Support up to 1080p 60 Hz for HDMI input
•Support up to 75 Mhz Pixel clock rate (8-bit 1080i/720p 60 Hz) in 24-bit mode and up to 150 Mhz Pixel clock rate (8-bit 1080p 60Hz YCC422) in Packed Pixel mode for MHL input
•Supports 24-bit color video output up to 1080p 60 Hz
•On-chip eDID RAM
•On-chip Audio Decoder which support 8-channel IIS/DSD and SPDIF audio outputs
•Supports Standard Audio, DSD Audio and HD (HBR) Audio
•Support audio soft mute
•Support SPDIF Channel Status extraction
•On-chip YCC422 to YCC444 conversion and YCC444 to YCC422 conversion
•On-chip YCC to RGB and RGB to YCC conversion in ITU-R BT.601 and 709 color space
•Support 24-bit RGB or 24-bit YCbCr 4:4:4 or 16-bit YCbCr 4:2:2 digital video output
•Support Bit Sequence Reverse and Port Swapping in video output ports to ease PCB layout
•Support DDR Clock in digital video outputs
•Register-programmable via slave IIC interface
•Flexible interrupt registers with interrupt pin
•Link On and Valid De Detection
•Controllable tri-state for output ports
•Low stand-by current (< 1mA) at power down mode
•128-pin LQFP

DIAGRAMMA A BLOCCHI