HD-, SD-SDI and DVB-ASI receiver, with integrated adaptive c'ble equalizer and audio processing
The GS1671A is a multi-rate SDI integrated Receiver which includes complete SMPTe processing, as per SMPTe 292M and SMPTe 259M-C. The SMPTe processing features can be bypassed to support signals with other coding schemes.
The GS1671A integrates Gennum's next-generation state-of-the-art adaptive cable equalizer technology, achieving unprecedented cable lengths and jitter tolerance. It features DC restoration to compensate for the DC content of SMPTe pathological signals.
The device features an Integrated Reclocker with an internal VCO and a wide Input Jitter Tolerance (IJT) of 0.7UI. A serial digital loop through output is provided, which can be configured to output either reclocked or non-reclocked serial digital data. The Serial Digital Output can be connected to an external Cable Driver.
The device operates in one of four basic modes: SMPTe mode, DVB-ASI mode, Data-Through mode or Standby mode.
In SMPTe mode, the GS1671A performs SMPTe de-scrambling and NRZI to NRZ decoding and word alignment. Line-based CRC errors, line number errors, TRS errors and ancillary data check sum errors can all be detected. The GS1671A also provides ancillary data extraction. The entire ancillary data packet is extracted, and written to host-accessible registers. Other processing functions include H:V:F timing extraction, Luma and Chroma ancillary data indication, video standard detection, and SMPTe 352M packet detection and decoding. All of the processing features are optional, and may be enabled or disabled via the Host Interface.
In DVB-ASI mode, 8b/10b decoding is applied to the received data stream.
In Data-Through mode, all forms of SMPTe and DVB-ASI decoding are disabled, and the device can be used as a simple serial to parallel converter.
The device can also be placed in a lower power Standby mode. In this mode, no signal processing is carried out and the parallel output is held static. Placing the Receiver in Standby mode will automatically place the integrated equalizer in power down mode as well.
Parallel data outputs are provided in 20-bit or 10-bit multiplexed format for HD and SD video rates. The associated Parallel Clock input signal operates at 148.5 or 148.5/1.001MHz (for all HD 10-bit multiplexed modes), 74.25 or 74.25/1.001MHz (for HD 20-bit mode), 27MHz (for SD 10-bit mode) and 13.5MHz (for SD 20-bit mode).
Up to eight channels, in two groups, of serial digital audio may be extracted from the video data stream, in accordance with SMPTe 272M and SMPTe 299M. The output signal formats supported by the device include AeS/eBU and three other industry standard serial digital formats. 16, 20 and 24-bit audio formats are supported at 48kHz synchronous for SD modes and 48kHz synchronous or asynchronous in HD mode. Additional audio processing features include group selection, channel swapping, eCC error detection and correction (HD mode only), and audio channel status extraction. Audio clock and control signals provided by the device include Word Clock (fs), Serial Clock (64fs), and Audio Master Clock at user-selectable rates of 128fs, 256fs or 512fs.
Features
Applications