eP965U is a 6G HDMI 2.0 transmitter with 8-lane cLVDS (Compressed LVDS) input and integrated HDCP 1.4/2.2 cypher. cLVDS is a super high speed LVDS technology developed by explore. The chip is compliant with HDMI 1.4/2.0 and HDCP 1.4/2.2 specifications. The chip converts video input data from 1 to 8 lanes cLVDS RX and audio input data in IIS, SPDIF, DSD or HBR format into HDMI differential signals.
eP965U is integrated with an on-chip eFlash MCU with pre-programmed firmware driver for HDCP 1.4/2.2 and HDMI 1.4/2.0 control. Software development effort can be greatly reduced.
Features
•HDMI Specification 1.4/2.0 Compliant
•HDCP Specification 1.4/2.2 Compliant
•Support TMDS Clock Frequency up to 600 MHz
•Support Video Pixel Clock Frequency up to 600 MHz
•Support cLVDS Data Bit Rate up to 5.4 GHz
•Support 1-lane, 2-lane, 4-land and 8-lane operation in cLVDS RX
•Support 3-byte, 4-byte, and 5-byte Data Packing mode in cLVDS RX
•Support 8-bit, 10-bit and 12-bit Deep Color modes
•Supports Pixel Repetition
•Support IIS, SPDIF (LPCM or compressed), DSD (Super Audio CD) and HBR (True HD Hight Bit Rate) audio types
•Support auto-send for DVI, ADO, ACR (Audio Clock Regeneration) and General Control packets.
•Support 3 Generic Data Packet buffers
•Support 1 port of SPDIF audio input (without the need for system clock), 4 ports of IIS audio inputs or 8 channels of DSD audio inputs
•Supports audio down sampling at 1/2, 1/3 or 1/4 sampling rate for both SPDIF and IIS
•Supports Receiver Hot Plug Detection and Receiver Connection Detection
•Downward compatible with DVI 1.0
•On-chip eFlash MCU with pre-programmed firmware driver for HDCP 1.4/2.2 and
HDMI 1.4/2.0 control
•Supports On-chip Test Pattern Generation (TPG) for production convenience.
•Supports Reverse Ordering for HDMI TX differential data pins for PCB layout flexibility
•Supports Power Down Mode
•3.3V, 1.3V and 1.2V power required
•100-Pin TQFP ePAD
Block Diagram
